发明名称 |
PMOS threshold voltage control by germanium implantation |
摘要 |
Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a P-active region in a silicon containing semiconducting substrate, performing an ion implantation process to implant germanium into the P-active region to form an implanted silicon-germanium region in the P-active region, and forming a gate electrode structure for a PMOS transistor above the implanted silicon-germanium region. |
申请公布号 |
US8828816(B2) |
申请公布日期 |
2014.09.09 |
申请号 |
US201113115428 |
申请日期 |
2011.05.25 |
申请人 |
GLOBALFOUNDRIES Inc. |
发明人 |
Javorka Peter;Kronholz Stephan |
分类号 |
H01L21/336;H01L29/66;H01L29/778;H01L21/8238;H01L21/265;H01L29/78;H01L29/165 |
主分类号 |
H01L21/336 |
代理机构 |
Amerson Law Firm, PLLC |
代理人 |
Amerson Law Firm, PLLC |
主权项 |
1. A method, comprising:
forming a P-active region and an N-active region in a semiconducting substrate comprising silicon; forming a masking layer that covers said N-active region and exposes the P-active region; with the masking layer in position, forming an implantation screen layer on said exposed P-active region; with the masking layer in position, performing an ion implantation process through said implantation screen layer to implant germanium into said P-active region to form an implanted silicon-germanium region in said P-active region, wherein performing said ion implantation process to implant germanium comprises performing said ion implantation process at an energy level ranging from 1-10 KeV with an implant dosage that ranges from 1e14-1e15 ions/cm2 of germanium; after performing said ion implantation process, removing said masking layer and said implantation screen layer so as to expose an upper surface of said P-active region; and forming a gate insulation layer of a gate electrode structure for a PMOS transistor on said exposed upper surface of said P-active region and on said implanted silicon-germanium region. |
地址 |
Grand Cayman KY |