Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof

摘要

A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects. The preparation method according to the present invention has a simple process, which is compatible with the CMOS process and is applicable to mass industrial production.

主权项

1. A preparation method of a silicon (Si)/germanium (Ge) heterojunction Tunnel Field Effect Transistor (TFET) comprising steps of:
Step 1: providing a Silicon On Insulator (SOI) substrate having top Si, a buried oxide layer and a back substrate, forming a silicon germanium (SiGe) layer and a surface Si layer successively on the top Si, and etching off peripheral parts of the SiGe layer and the surface Si layer according to a preset size, so as to form a mesa structure stacked by the SiGe layer and the surface Si layer on the surface of the top Si; Step 2: forming a SiO2 layer on the entire surface of the mesa structure, then forming a silicon nitride (Si3N4) layer on the surface of the silicon dioxide (SiO2) layer, and finally etching off Si3N4 on the top of the mesa structure; Step 3: performing oxidizing and annealing on the mesa structure to oxidize the surface Si layer and gradually oxidize the SiGe layer and the top Si, so that Ge in the SiGe layer is longitudinally diffused toward the top Si and gradually concentrated, and is laterally diffused in the top Si to form a Ge/Si heterojunction structure with a gradient Ge content, so as to prepare a SiGe or Ge region; Step 4: removing the Si3N4 layer and the SiO2 layer, polishing the surfaces of the top Si and the SiGe or Ge region, and then manufacturing an isolation trench at a preset position to form a SiGe or Ge region and a Si region for preparing a device; and Step 5: manufacturing a gate, and manufacturing a source region and a drain region using a self-aligned process, wherein the source region is located in the SiGe or Ge region, the drain region is located in the Si region, and the gate covers both a part of the SiGe or Ge region and a part of the Si region.