发明名称 Programmable micro-core processors for security processing
摘要 A security processing system includes one or more micro-cores that can operate in conjunction with one or more security cores to process packets. The micro-core can perform any suitably programmed tasks upon packets, such as encryption/decryption and authentication tasks. The combination of having both the hard-coded security engines and the programmable micro-core within the same system permits the security system to effectively obtain the benefit of the speed and performance advantages of having dedicated security hardware, in addition to the flexibility and expandability of being able to use a programmable micro-core.
申请公布号 US8832776(B1) 申请公布日期 2014.09.09
申请号 US201113164565 申请日期 2011.06.20
申请人 Broadcom Corporation 发明人 Natarajan Revathi
分类号 G06F21/00 主分类号 G06F21/00
代理机构 Sterne, Kessler, Goldstein & Fox P.L.L.C. 代理人 Sterne, Kessler, Goldstein & Fox P.L.L.C.
主权项 1. A system for performing security processing, comprising: a first security circuit that is hardcoded with a first set of security functionality to address a first specific security protocol, and that has an input and an output; a second security circuit that is hardcoded with a second set of security functionality to address a second specific security protocol, and that has an input and an output; a micro-core that is programmable to implement a third set of security functionality, and that has an input and an output; a first multiplexer having a first input coupled to the output of the micro-core, and an output coupled to the input of the first security circuit; a memory having an output coupled to a second input of the first multiplexer and to the input of the micro-core; a second multiplexer having a first input coupled to the output of the first security circuit, a second input coupled to the output of the first multiplexer, a third input coupled to the output of the micro-core, and an output coupled to the input of the micro-core; a third multiplexer having a first input coupled to the output of the first multiplexer, a second input coupled to the output of the second multiplexer, a third input coupled to the output of the micro-core, and an output coupled to the input of the second security circuit; wherein the micro-core is configured to execute program code with deterministic latency.
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