Method and apparatus for improving CMP planarity

摘要

Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.

主权项

1. A method of fabricating a semiconductor device, comprising:
forming an interconnect structure over a wafer; performing a first planarization process to expose the interconnect structure, wherein the interconnect structure has an uneven topography after the first planarization process; forming a sacrificial layer over the interconnect structure after the first planarization process, wherein the sacrificial layer is formed to have a substantially planar surface profile; and performing a second planarization process to expose the interconnect structure, wherein the second planarization process removes the sacrificial layer and a portion of the interconnect structure therebelow, and wherein the second planarization process is performed in a manner such that the substantially planar surface profile is transferred to the interconnect structure after the second planarization process.