Storage devices with secure debugging capability and methods of operating the same

摘要

A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.

主权项

1. A device comprising:
a first bus; a storage circuit coupled to the first bus; an authentication circuit coupled to the first bus; a second bus separate from the first bus; a debug control circuit coupled to the second bus and configured to transmit data to a debug host via a transmit channel and to receive data from the debug host over a receive channel; a processor configured to communicate with the storage circuit and the authentication circuit through the first bus and to communicate with the debug control circuit through the second bus wherein the debug control circuit is configured to detect an attachment of the debug host and, responsive to detecting the attachment, to inhibit transfer of data from the second bus to the debug host via the transmit channel while allowing authentication information received from the debug host over the receive channel to be transferred to the authentication circuit via the first and second buses, and to continue inhibiting transfer of data from the second bus to the debug host via the transmit channel until the authentication information received from the debug host is authenticated by the authentication circuit.