Retiming-based design flow for delay recovery on inter-die paths in 3D ICs

摘要

A three dimensional (3D) stacked integrated circuit (IC) design-for-Testing (DfT) die-level wrapper boundary register having a bypass mode and design-level DfT delay recovery techniques are provided. Die wrappers that contain boundary registers at the interface between dies can be inserted into 3D ICs where the boundary registers include a gated scan flop with a bypass line passing the functional input to a through-silicon-via (TSV) in a manner avoiding the clocked stages of the gated scan flop during functional operation. A retiming process can be applied during design layout using a simulation/routing tool or standalone program to recover the additional delay added to the TSV paths by the DfT insertion. Retiming can be performed at both die and stack level, and in further embodiments, logic redistribution across adjacent dies of the stack can be performed for further delay optimization.

主权项

1. A method of delay recovery for a 3D IC comprising a stack of at least two dies and having a design-for-testing (DfT) die wrapper with boundary registers, the method comprising:
applying a retiming process after die wrapper insertion to a synthesized register transfer level (RTL) design of the 3D IC, wherein boundary registers of the die wrapper located between a logic block and a through-silicon-via (TSV) are set as a fixed register so that the boundary register is not moved and logic or another register is not moved between the boundary register and the TSV during the retiming process.