发明名称 |
Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode |
摘要 |
Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region. |
申请公布号 |
US8828819(B2) |
申请公布日期 |
2014.09.09 |
申请号 |
US201213718346 |
申请日期 |
2012.12.18 |
申请人 |
GLOBALFOUNDRIES Inc. |
发明人 |
Kronholz Stephen;Lenski Markus;Papageorgiou Vassilios |
分类号 |
H01L27/092;H01L21/336;H01L29/49;H01L29/423;H01L21/28;H01L21/8234;H01L21/8238;H01L29/78 |
主分类号 |
H01L27/092 |
代理机构 |
Amerson Law Firm, PLLC |
代理人 |
Amerson Law Firm, PLLC |
主权项 |
1. A method, comprising:
forming a gate layer stack above a first semiconductor region and a second semiconductor region; patterning said gate layer stack to form a first gate electrode structure above said first semiconductor region and a second gate electrode structure above said second semiconductor region, an upper portion of said first gate electrode structure having a first target gate length, a lower portion of said first gate electrode structure adjacent to said first semiconductor region having a first effective gate length that is less than said first target gate length, and a lower portion of said second gate electrode structure having a second effective gate length adjacent to said second semiconductor region that is greater than said first effective gate length; forming a spacer layer above said first and second gate electrode structures, said spacer layer having a thickness of approximately 10 nm or less; forming a spacer element on sidewalls of said first gate electrode structure from said spacer layer; and forming a strain-inducing semiconductor alloy in said first semiconductor region by using said spacer element as a mask. |
地址 |
Grand Cayman KY |