Non-volatile memory array partitioning architecture and method to utilize single level cells and multi-level cells within the same memory

摘要

A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.

主权项

1. A memory device, comprising:
an array of memory cells; and a partitioning system configured to address a first portion of the array in a single level cell mode and a second portion of the array in a multi-level cell mode, wherein the partitioning system is configured to distinguish between the first and second portions based on first and second programmable address pointers provided thereto, wherein the partitioning system identifies all the memory cells in the array having addresses between the first and second programmable address pointers as the first portion and all remaining memory cells in the array as the second portion, and wherein the first and second programmable address pointers comprise adjustable addresses stored in first and second registers, respectively, that are adjustable by a user input, thereby making the partitioning system configurable.