| 发明名称 | First-in-first-out queue-based command spreading | ||
| 摘要 | Embodiments relate to first-in-first-out (FIFO) queue based command spreading. An aspect includes receiving a plurality of commands by a first level priority stage of a memory control unit (MCU), wherein each of the plurality of commands is associated with one of a plurality of ports located on a buffer chip. Another aspect includes storing each of the plurality of commands in a FIFO queue of a plurality of FIFO queues in the MCU, wherein each of the plurality of commands is assigned to a FIFO queue based on the command's associated port, and each of the plurality of FIFO queues is associated with a respective one of the plurality of ports located on the buffer chip. Another aspect includes selecting a FIFO queue of the plurality of FIFO queues and forwarding a command from the selected FIFO queue to the buffer chip by the second level priority stage. Another aspect includes a third level priority on the buffer chip associated with each respective FIFO queue to help optimize the bandwidth on the returning upstream fetch bus. | ||
| 申请公布号 | US8832324(B1) | 申请公布日期 | 2014.09.09 |
| 申请号 | US201313835205 | 申请日期 | 2013.03.15 |
| 申请人 | International Business Machines Corporation | 发明人 | Hodges Mark R.;Papazova Vesselina K.;Meaney Patrick J. |
| 分类号 | G06F13/368;G06F13/18;G06F3/06 | 主分类号 | G06F13/368 |
| 代理机构 | Cantor Colburn LLP | 代理人 | Cantor Colburn LLP ;McNamara Margaret |
| 主权项 | 1. A computer implemented method for first-in-first-out (FIFO) queue based command spreading in a memory control unit (MCU), the method comprising: receiving a plurality of commands from one or more command queues by a first level priority stage of the MCU, wherein each of the plurality of commands is associated with one of a plurality of ports located on a buffer chip that is in communication with the MCU; storing each of the plurality of commands in a FIFO queue of a plurality of FIFO queues in the MCU, wherein each of the plurality of commands is assigned to a FIFO queue based on the command's associated port, and each of the plurality of FIFO queues is associated with a respective one of the plurality of ports located on the buffer chip; selecting, by a second level priority stage of the MCU, a FIFO queue of the plurality of FIFO queues; and forwarding a command from the selected FIFO queue to the buffer chip by the second level priority stage. | ||
| 地址 | Armonk NY US | ||