发明名称 Data transfer device and data transfer system
摘要 A transfer device according to an embodiment transfers blocks generated by dividing a frame into pieces of data and adding a synchronization header each of the pieces of data. The blocks comprise a first, second and third blocks in this order. The transfer device is configured to acquire a first synchronization header in the first block, a second synchronization header in the second block and a third synchronization header in the third block, judge, in a case where a value of the second synchronization header is incorrect, as to whether or not the value of the second synchronization header can be estimated based on the first and the third synchronization headers so that the second block is consistent with the first and third blocks, and correct the second synchronization header into the estimated value.
申请公布号 US8831040(B2) 申请公布日期 2014.09.09
申请号 US201113021550 申请日期 2011.02.04
申请人 Hitachi, Ltd. 发明人 Nakajima Tetsuya;Shibasaki Masatoshi;Tamura Yukihisa
分类号 H04J3/06;H04L1/00 主分类号 H04J3/06
代理机构 Foley & Lardner LLP 代理人 Foley & Lardner LLP
主权项 1. A data transfer device for transferring blocks generated by dividing a frame into pieces of data each having a first predetermined number of bits and adding a synchronization header having a second predetermined number of bits to each of the blocks, comprising: a processing module configured to process an operation of the data transfer device; a buffer for storing the blocks to be transferred; and an interface configured to receive and transmit data to and from the data transfer device, wherein: the synchronization header is configured for synchronization of each of the blocks and has first information for identifying whether the respective block includes a control code other than user data; wherein the blocks comprise a first block, a second block, and a third block that are successively transferred in the stated order; the first block, the second block and the third block include a first synchronization header, a second synchronization header and a third synchronization header as the synchronization header, respectively; and the processing module is configured to: acquire the first synchronization header, the second synchronization header, and the third synchronization header;perform, in a case where a value of the first information of the second synchronization header is incorrect, a first judgment as to whether or not the value of the first information of the second synchronization header can be estimated based on the first synchronization header and the third synchronization header so that the second block is consistent with the first block and the third block;judge, in a case where a value of the first information of the first synchronization header and a value of the first information of the third synchronization header is same, that the second synchronization header can be estimated in the first judgment; andcorrect the second synchronization header into an estimated value of the first information.
地址 Tokyo JP