发明名称 MEMORY SYSTEM COMPRISING ECC BLOCK FOR REDUCING A LATENCY AND ERROR CORRECTION METHOD THEREOF
摘要 An error correction decoder includes a syndrome computation circuit, an error correction and computation circuit and an error correction circuit. The syndrome computation circuit calculates a syndrome of read data. The error correction and computation circuit calculates a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data. The error correction circuit corrects the single-bit error of the read data based on the location of the single-bit error.
申请公布号 KR101437396(B1) 申请公布日期 2014.09.05
申请号 KR20080017972 申请日期 2008.02.27
申请人 发明人
分类号 G11C29/42 主分类号 G11C29/42
代理机构 代理人
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