发明名称 |
PERIPHERAL ELECTRICAL CONNECTION OF PACKAGE ON PACKAGE |
摘要 |
<p>According to various embodiments of a mechanism that a die package is formed using a through sidewall via (TsV) which is formed by sawing a through substrate via (TSV) in half, various semiconductor dies and passive components may be electrically connected to achieve targeted electrical performance at edges of a described die. A redistribution structure with a redistribution layer (RDL) is used along with the TsV to facilitate the electrical connection. Since the TsV is away from a device region, the device region does not receive the stress caused by the TSV formation. In addition, electrical connection between upper and lower dies by the TsV increases the efficiency of the area utilization of the die package.</p> |
申请公布号 |
KR20140107074(A) |
申请公布日期 |
2014.09.04 |
申请号 |
KR20130058503 |
申请日期 |
2013.05.23 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
HSIAO CHING WEN;LIN CHIH WEI;CHANG WEI SEN;HU YEN CHANG;PAN KUO LUNG;HUANG YU CHIH |
分类号 |
H01L23/48;H01L23/12 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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