METHOD AND CIRCUIT STRUCTURE FOR SUPPRESSING SINGLE EVENT TRANSIENTS OR GLITCHES IN DIGITAL ELECTRONIC CIRCUITS

摘要

A circuit structure (200) for suppressing single event transients (SETs) or glitches in digital electronic circuits is provided. The circuit structure includes a first input (100) which receives an output of a digital electronic circuit (A), a second input (100′) which receives a redundant or duplicated output of the digital electronic circuit (A′), and two sub-circuits (102, 106) that each receive the inputs and have one output. One of the sub-circuits is insensitive to a change in the value of one of its inputs when the inputs are in a first logic state and the other sub-circuit is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state. The sub-circuit outputs are input into a two-input multiplexer (202) which has its output (204) connected to its selection port (SEL), and the sub-circuits are arranged so that the sub-circuit which is insensitive to a change in the value of one of its inputs is selected whenever the output of the multiplexer changes. The multiplexer output (204) is provided as a final output in which SETs and glitches have been suppressed.

主权项

1. A circuit structure for suppressing single event transients (SETs) or glitches in digital electronic circuits, comprising:
a first input which receives an output of a digital electronic circuit; a second input which receives a redundant or duplicated output of the digital electronic circuit; two sub-circuits that each receive the first and second inputs and each have one output; wherein the output of one of the sub-circuits is insensitive to a change in the value of one of the inputs when the inputs are in a first logic state, and wherein the output of the other of the sub-circuits is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state; a two-input multiplexer which receives the outputs of the two sub-circuits as the multiplexer's inputs and selects one of the multiplexer's inputs as its output; wherein the selected multiplexer input is determined by the logic value of the output of the multiplexer and the two sub-circuits are arranged so that the output of the sub-circuit which is insensitive to a change in the value of one of the inputs is selected whenever the output of the multiplexer changes; so that the output of the multiplexer is always insensitive to an SET or glitch in the digital electronic circuit that may result in a temporary change in the logic value of either the first input or the second input; the output of the multiplexer being provided as a final output of the digital electronic circuit in which SETs and glitches have been suppressed.