Erase For 3D Non-Volatile Memory With Sequential Selection Of Word Lines

摘要

An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.

主权项

1. A method for performing an erase operation, comprising:
pre-charging a channel of an active area of a plurality of selected memory cells, the pre-charging of the channel comprises applying a pre-charge voltage to one end of the active area, the plurality of selected memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory; and subsequently, for each selected memory cell of the plurality of selected memory cells, erasing the memory cell by applying an erase voltage, higher than the pre-charge voltage, to the one end of the active area to charge the channel higher while configuring a control gate voltage of the selected memory cell to encourage erasing of the selected memory cell in an erase period, a timing of the erase period is based on a position of the selected memory cell in the active area.