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1. A converter comprising:
a bridge comprising:
an AC terminal for each of at least one AC line;a first DC terminal and a second DC terminal;a first converter arm connected between each respective AC terminal and the first DC terminal; anda second converter arm connected between each respective AC terminal and the second DC terminal, each converter arm comprising at least one first power semiconductor switching device configured to be turned ‘on’ and ‘off’ by gate control, and have a recovery time, wherein the converter is configured to operate in at least one of the following inverting modes:
(a) a first naturally commutated inverting mode wherein, during each commutation event, an incoming first power semiconductor switching device is turned ‘on’ by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in an outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor device is turned ‘off’ by gate control at the reference time, and the available circuit commutated turn-off time is greater than the recovery time that is applicable with an open circuit gate terminal bias applied,(b) a second naturally commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘on’ by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘off’ by gate control at the reference time, and the available circuit commutated turn-off time is shorter than the recovery time that is applicable with an open circuit gate terminal bias applied, the available circuit commutated turn-off time optionally being zero or close to zero, and(c) a combined naturally commutated and gate commutated inverting mode wherein, during each commutation event, the incoming first power semiconductor switching device is turned ‘on’ by gate control at a point in time in advance of a reference time such that anode current in the incoming first power semiconductor switching device increases at a determined rate and anode current in the outgoing first power semiconductor switching device decreases at a determined rate, the outgoing first power semiconductor switching device is turned ‘off’ by gate control at the reference time or at a point in time that is delayed beyond the reference time, and the available circuit commutated turn-off time is less than zero. |
