发明名称 |
Programmable Leakage Test For Interconnects In Stacked Designs |
摘要 |
Aspects of the invention relate to techniques of testing interconnects in stacked designs for leakage defects. Logic “1” or “0” is first applied to one end of an interconnect during a first pulse. Then, logic value at the one end is captured, which triggered by an edge of a second pulse. The first pulse precedes the second pulse by a time period being selected from a plurality of delay periods. The plurality of delay periods is generated by a device shared by a plurality of interconnects. |
申请公布号 |
US2014246705(A1) |
申请公布日期 |
2014.09.04 |
申请号 |
US201414195639 |
申请日期 |
2014.03.03 |
申请人 |
Mentor Graphics Corporation |
发明人 |
Huang Shi-Yu;Tsai Kun-Han;Cheng Wu-Tung;Lin Yu-Hsiang;Huang Li-Ren |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Wilsonville OR US |