| 发明名称 |
MINIMIZING POWER CONSUMPTION IN ASYNCHRONOUS DATAFLOW ARCHITECTURES |
| 摘要 |
A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein. |
| 申请公布号 |
US2014247088(A1) |
申请公布日期 |
2014.09.04 |
| 申请号 |
US201313782631 |
申请日期 |
2013.03.01 |
| 申请人 |
RAYTHEON COMPANY |
发明人 |
Prager Kenneth E.;Lewins Lloyd J.;Marr Harry;Karl Julia;Vahey Michael |
| 分类号 |
H03K19/00 |
主分类号 |
H03K19/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A digital signal processing apparatus, comprising:
a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein. |
| 地址 |
Waltham MA US |
