| 摘要 |
<p>An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.</p> |
