| 摘要 |
The present invention relates to a memory circuit integrated in each pixel of a display device includes a switching circuit and a memory unit. The switching circuit includes a first transistor having a gate configured to receive a switching control signal, a source and a drain electrically coupled to a liquid crystal capacitor of the pixel, and a second transistor having a gate configured to receive a switching control signal, a source electrically coupled to a storage capacitor of the pixel, and a drain electrically coupled to the liquid crystal capacitor. The memory unit is electrically coupled between the source of first transistor and the storage capacitor. The switching control signal is configured such that in the normal mode, the first transistor is turned off, while the second transistor is turned on, so that the storage capacitor is electrically coupled to the liquid crystal capacitor in parallel and the memory unit is bypassed, and in the still mode, the first transistor is turned on, while the second transistor is turned off, so that the storage capacitor controls the memory unit to supply a stored data to the liquid crystal capacitor. |
| 主权项 |
1. A memory circuit integrated in each pixel of a display device, wherein each pixel comprises a pixel switch, Pixel_SW, and a liquid crystal capacitor, Clc, electrically coupled to the pixel switch, Pixel_SW, and a storage capacitor, Cst, and operably alternates in a normal mode in which the pixel switch Pixel_SW is tuned on and a still mode in which the pixel switch Pixel_SW is tuned off, comprising:
(a) a switching circuit comprising:
a first transistor, SW1, having a gate configured to receive a switching control signal, EN/EN_P, a source and a drain electrically coupled to the liquid crystal capacitor Clc;a second transistor, SW2, having a gate configured to receive a switching control signal, EN/EN_P, a source electrically coupled to the storage capacitor Cst, and a drain electrically coupled to the liquid crystal capacitor Clc; anda third transistor, SW3, having a gate configured to receive the switching control signal, EN/EN_P, a source and a drain electrically coupled to the storage capacitor Cst; and (b) a memory unit electrically coupled between the source of first transistor SW1 and the source of the third transistor SW3 of the switching circuit, wherein the switching control signal EN/EN_P is configured such that in the normal mode, the first transistor SW1 and the third transistor SW3 are turned off, while the second transistor SW2 is turned on, so that the storage capacitor Cst is electrically coupled to the liquid crystal capacitor Clc in parallel and the memory unit is bypassed, and in the still mode, the first transistor SW1 and the third transistor SW3 are turned on, while the second transistor SW2 is turned off, so that the storage capacitor Cst controls the memory unit to supply a stored data to the liquid crystal capacitor Clc. |
