Multiple signal format output driver with configurable internal load

摘要

A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal.

主权项

1. An integrated circuit comprising:
a first output node; a second output node; and a multiple signal format output driver comprising:
a differential circuit configured to provide a differential signal to the first output node and the second output node; anda load circuit comprising
a first resistor and a second resistor;a first switch coupled to the first resistor and a regulated voltage node;a second switch coupled to the second resistor and the regulated voltage node; anda third switch coupled to the first resistor, the second resistor, the first switch, and the second switch, the load circuit being configurable in response to one or more first values of a control signal to couple the first resistor between the first output node and the regulated voltage node and to couple the second resistor between the second output node and the regulated voltage node, the load circuit being configurable in response to one or more second values of the control signal to couple the first resistor between the first output node and the third switch and to couple the second resistor between the second output node and the third switch.