发明名称 Graphics tiling architecture with bounding volume hierarchies
摘要 In some embodiments, tile lists may be avoided by storing the geometry of a scene in a bounding volume hierarchy (BVH). For each tile, the bounding volume hierarchy is traversed. The traversals continued only into children nodes that overlap with the frustum on the tile. By relaxing the ordering constraint of rendering primitives, the BVH is traversed such that nodes that are closer to the viewer are traversed first, increasing the occlusion culling efficiency in some embodiments. Rendering the full scene between the central processing cores and the graphics processor may be done through a shared memory in some embodiments.
申请公布号 US8823736(B2) 申请公布日期 2014.09.02
申请号 US201213354712 申请日期 2012.01.20
申请人 Intel Corporation 发明人 Barringer Rasmus;Gribel Carl Johan;Lefohn Aaron;Akenine-Möller Tomas G.
分类号 G09G5/00 主分类号 G09G5/00
代理机构 Trop, Pruner & Hu, P.C 代理人 Trop, Pruner & Hu, P.C
主权项 1. A method comprising: storing, using a computer processor, scene geometry in a bounding volume hierarchy; traversing the bounding volume hierarchy for each tile of a plurality of tiles; continuing the traversal only into child nodes that overlap with a frustum of a tile; and performing back-end rasterization when a leaf node is reached.
地址 Santa Clara CA US