发明名称 Grid refinement method
摘要 The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.
申请公布号 US8822107(B2) 申请公布日期 2014.09.02
申请号 US201313754840 申请日期 2013.01.30
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Wang Wen-Chuan;Lin Shy-Jay;Liu Pei-Yi;Shin Jaw-Jung;Lin Burn Jeng
分类号 G03F1/20;G03F7/20 主分类号 G03F1/20
代理机构 Haynes and Boone, LLP 代理人 Haynes and Boone, LLP
主权项 1. A method for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1, comprising: providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.
地址 Hsin-Chu TW