Reduced pin count interface

摘要

An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.

主权项

1. A memory device adapted for connection with a controller and one or more other memory devices arranged in a ring topology, said memory device comprising a data input connection for receiving device address assignment commands and a data output connection for forwarding said device address assignment commands, where said device address assignment commands include to-be-assigned device addresses, and said memory device being adapted to:
receive, from the controller, a first one of said device address assignment commands on said data input connection; record a to-be-assigned device address of said first one of said device address assignment commands; receive, from the controller, a subsequent one of said device address assignment commands on said data input connection; and forward said subsequent one of said device address assignment commands on said data output connection.