发明名称 |
Digital phase detector with zero phase offset |
摘要 |
An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal. |
申请公布号 |
US8824573(B2) |
申请公布日期 |
2014.09.02 |
申请号 |
US201414150508 |
申请日期 |
2014.01.08 |
申请人 |
International Business Machines Corporation |
发明人 |
Dreps Daniel M.;Kim Kyu-hyoun;Wiedemeier Glen A. |
分类号 |
H04L27/00 |
主分类号 |
H04L27/00 |
代理机构 |
|
代理人 |
Pennington Joan |
主权项 |
1. A communication system comprising:
a first processor comprising a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector to receive a clock signal and to generate one or more delayed clock signals, a control signal, and a gated data signal; and a second processor coupled to the first processor, the second processor to receive the control signal and the gated data signal. |
地址 |
Armonk NY US |