| 发明名称 | Data output circuit | ||
| 摘要 | A data output circuit according to one embodiment of the present invention includes: a delay control block configured to generate a clock delay signal in response to a power-up signal and a reset signal; a first delay block configured to correct a duty ratio of a rising clock according to the clock delay signal and output the corrected rising clock; and a second delay block configured to correct a duty ratio of a falling clock according to the clock delay signal and output the corrected falling clock. | ||
| 申请公布号 | US8823433(B2) | 申请公布日期 | 2014.09.02 |
| 申请号 | US201313846547 | 申请日期 | 2013.03.18 |
| 申请人 | SK Hynix Inc. | 发明人 | Cha Jin Youp;Cho Jin Hee;Kim Jae Il |
| 分类号 | H03K7/08;H03K3/011 | 主分类号 | H03K7/08 |
| 代理机构 | William Park & Associates Ltd. | 代理人 | William Park & Associates Ltd. |
| 主权项 | 1. A data output circuit comprising: a delay control block configured to generate a clock delay signal in response to a power-up signal and a reset signal; a first delay block configured to correct a duty ratio of a rising clock according to the clock delay signal and output the corrected rising clock; and a second delay block configured to correct a duty ratio of a falling clock according to the clock delay signal and output the corrected falling clock wherein the delay control block includes a monitoring section configured to monitor skew of a PMOS transistor and an NMOS transistor of the delay control block. | ||
| 地址 | Gyeonggi-do KR | ||