Data storage circuit that retains state during precharge

摘要

A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.

主权项

1. A data storage circuit for receiving and holding a data value, said data storage circuit comprising:
an input stage configured to be precharged during a precharge phase, to receive a data value in response to said precharge phase changing to an evaluation phase and to hold said data value during said evaluation phase, said input stage comprises an input latching element for holding said data value and dual data lines for outputting said data value and an inverse version of said data value to an output stage, said input latching element being configured to output a logical one on both of said dual data lines during said precharge phase and to output said data value during said evaluation phase by discharging one of said dual data lines to a logical zero; said output stage for holding a value dependent on said data value received from said dual data lines; wherein said output stage comprises an output latching element for holding said value, two switching devices for updating said output latching element and an output, said two switching devices each being controlled by respective signals from said dual data lines, such that: in response to said data value held in said input stage being a logical one, a first switching device of said two switching devices updates said output latching element with a value indicative of said logical one; in response to said data value held in said input stage being a logical zero, a second switching device of said two switching devices updates said output latching element with a value indicative of said logical zero; in response to said dual data lines both outputting a logical one, said two switching devices do not supply a logical value to said output latching element such that said output latching element continues to hold a previously held value; and said output latching element comprises an inverter and a tristate inverter arranged to form a feedback loop, said tristate inverter being controlled by a signal received from one of said dual data lines and an inverted signal received from an other of said dual data lines, such that during said precharge stage when said dual data lines output logical ones said tristate inverter is driving and said output latching element holds a previously held value, and in response to one of said dual data lines falling to a logical zero indicating a data value, a portion of said tristate converter is turned off and said output latching element is updated to store said value dependent on said data value.