Matrix display device with cascading pulses and method of driving the same

摘要

In a plurality of source drivers, a unit start pulse inputted/outputted to/from the source drivers is cascaded between an ante-stage source driver and a post-stage source driver, a horizontal start pulse outputted from a timing controller is inputted to a first-stage source driver, and the duty ratio of a vertical clock is controlled by one of the plurality of cascaded unit start pulses. In a matrix display device, it is thereby possible to provide a timing controller having a simple circuit configuration which needs no counter circuit for generating a vertical clock to be outputted to a gate driver.

主权项

1. A matrix display device, comprising:
a matrix board in which a plurality of pixels surrounded by m scanning lines and n video signal lines are arranged in matrix, for controlling a plurality of pixel transistors connected to said pixels on conduction by a gate signal supplied through said scanning lines and supplying a pixel writing voltage supplied through said video signal lines to said pixels through said pixel transistors; a scanning line drive circuit for supplying said gate signal to said scanning lines; a plurality of video signal line drive circuits for supplying said pixel writing voltage to said video signal lines; and a timing controller for outputting a display control data signal including a shift start pulse to said video signal line drive circuits and outputting a horizontal scan control signal including a vertical clock to said scanning line drive circuit, wherein each of unit start pulses inputted/outputted to/from said plurality of video signal line drive circuits is cascaded between an ante-stage video signal line drive circuit and a post-stage video signal line drive circuit in said plurality of video signal line drive circuits, said shift start pulse outputted from said timing controller is inputted to a first-stage video signal line drive circuit, the duty ratio of said vertical clock is controlled by one of said plurality of cascaded unit start pulses, and the duty ratio of said vertical clock that is controlled by said one of said plurality of cascaded unit start pulses is fixed during a vertical display period.