Automating current-aware integrated circuit and package design and optimization

摘要

A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

主权项

1. A computer-implemented method for automated integrated circuit chip design comprising:
generating, at a computer system, a data structure representing a current distribution relation between one or more current sources and one or more physical structures that deliver electrical current drawn by said current sources as connected via grid networks; and evaluating, using said data structure, a chip design, said chip design evaluating comprising:
quantifying an amount of current flowing through physical structures under one or more operating conditions, said operating conditions represented by a set of vectors of current, Is, drawn by the current sources, andsaid quantifying the amount of current flowing through physical structures as a product of the set of vectors of current drawn by the current sources and the current distribution relation data structure; the computer system having a memory device and a programmed processing unit configured to perform said generating and evaluating and optimizing.