Accumulating LDPC (low density parity check) decoder

摘要

Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.

主权项

1. A communication device comprising:
an input configured to receive an low density parity check (LDPC) coded signal via a communication channel from another communication device; and a processor configured to:
update a first plurality of APP (a posteriori probability) values to generate a second plurality of APP values based on a plurality of differences between a first and a second plurality of check edge messages such that no more than one APP value within any column of an LDPC matrix of the LDPC coded signal is updated during a clock cycle; andgenerate a plurality of estimates of bits encoded within the LDPC coded signal using the second plurality of APP values.