发明名称 Bus apparatus with default speculative transactions and non-speculative extension
摘要 A bus apparatus is provided, which includes a bus master and a bus slave coupled to the bus master through a bus interface. When the bus master sends a bus transaction to the bus slave, the bus slave executes the bus transaction. The bus transaction is speculative by default. The command of the bus transaction indicates whether the bus transaction is a write transaction or a read transaction. When the bus transaction is a write transaction, the bus slave stores the write data of the bus transaction at the address of the bus transaction. When the bus transaction is a read transaction, the bus slave responds the bus transaction with a read data stored at the address of the bus transaction. The bus slave informs the bus master that the bus slave will not recognize further bus transactions in a specific period of time by asserting a bus wait signal.
申请公布号 US8825933(B2) 申请公布日期 2014.09.02
申请号 US201113307007 申请日期 2011.11.30
申请人 Andes Technology Corporation 发明人 Lai Chi-Chang
分类号 G06F13/00 主分类号 G06F13/00
代理机构 Jianq Chyun IP Office 代理人 Jianq Chyun IP Office
主权项 1. A bus apparatus, comprising: a bus master; and a bus slave coupled to the bus master through a bus interface, wherein when the bus master sends a bus transaction to the bus slave, the bus slave executes the bus transaction, wherein the bus transaction is speculative by default and a command of the bus transaction indicates whether the bus transaction is a write transaction or a read transaction; when the bus transaction is the write transaction, the bus slave stores a write data of the bus transaction at an address of the bus transaction; when the bus transaction is the read transaction, the bus slave responds the bus transaction with a read data stored at the address of the bus transaction; the bus slave informs the bus master that the bus slave will not recognize further bus transactions in a specific period of time by asserting a bus wait signal.
地址 Hsin-Chu TW