发明名称 Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
摘要 A multi-layer printed circuit board including a core substrate, lower interlayer resin insulating layers formed on the surfaces of the core substrate, respectively, through-hole conductors formed in penetrating holes penetrating through the core substrate and the lower interlayer resin insulating layers, conductor circuits formed on the lower interlayer resin insulating layers, respectively, upper interlayer resin insulating layers formed on the conductor circuits and the lower interlayer resin insulating layers, respectively and via hole conductors formed in the upper interlayer resin insulating layers and positioned on the through-hole conductors, respectively.
申请公布号 US8822839(B2) 申请公布日期 2014.09.02
申请号 US201113307213 申请日期 2011.11.30
申请人 Ibiden Co., Ltd. 发明人 Kawasaki Yogo;Satake Hiroaki;Iwata Yutaka;Tanabe Tetsuya
分类号 H05K1/11 主分类号 H05K1/11
代理机构 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A multi-layer printed circuit board, comprising: a core substrate having a first surface and a second surface on an opposite side of the first surface; a plurality of interlayer resin insulating layers including a plurality of lower interlayer resin insulating layers formed on the first and second surfaces of the core substrate, respectively, and a plurality of upper interlayer resin insulating layers formed on the lower interlayer resin insulating layers, respectively; a plurality of through-hole conductors formed in a plurality of penetrating holes penetrating through the core substrate and the lower interlayer resin insulating layers and including a plurality of first through-hole conductors and a plurality of second through-hole conductors; a plurality of conductor circuits formed on the lower interlayer resin insulating layers, respectively, and interposed between the lower interlayer resin insulating layers and upper interlayer resin insulating layers, respectively; a plurality of via-hole conductors including a plurality of lower via-hole conductors formed in the lower interlayer resin insulating layers and a plurality of upper via-hole conductors formed in the upper interlayer resin insulating layers; and a conductor pattern formed on one of the first and second surfaces of the core substrate and connecting the first through-hole conductors and the lower via-hole conductors, respectively, wherein the lower via-hole conductors are connected to the conductor circuits formed on the lower interlayer resin insulating layers, respectively, and positioned such that the plurality of lower via-hole conductors corresponds with a plurality of first external connection terminals, respectively.
地址 Ogaki-shi JP