Method and apparatus for parallelization of sequential power simulation

摘要

One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at the same time, thereby reducing he required time necessary to perform the power simulation. More particularly, a logic simulation may be performed on the integrated circuit and snapshots of the logic devices of the integrated circuit may be taken at a specified period. The separate time segments of the simulation may then be simulated in a parallel manner to simulate power consumption of the integrated circuit. Performing the power simulation on the separate time segments may reduce the required time of a typical power consumption simulation of an integrated circuit.

主权项

1. A method for conducting a power consumption simulation of an integrated circuit, the method comprising:
dividing a serial power consumption simulation of the integrated circuit into a plurality of time segments based on a specified number of clock cycles by:
performing a forward-progressing logic simulation of the integrated circuit;extracting first state information of a plurality of logic devices of the integrated circuit after the logic simulation is performed for a first time segment equal to the specified number of clock cycles;extracting second state information of the plurality of logic devices of the integrated circuit after the logic simulation is performed for a second time segment equal to the specified number of clock cycles;initializing a first representation of the plurality of logic devices of the integrated circuit according to the first extracted state information;initializing a second representation of the plurality of logic devices of the integrated circuit according to the second extracted state information;simulating power consumption of the first representation of the plurality of logic devices and the second representation of the logic devices simultaneously on a plurality of separate simulation benches; andaggregating results of simulations of the integrated circuit for the plurality of time segments.