| 发明名称 |
METHODS AND APPARATUS RELATED TO CAPACITANCE REDUCTION OF A SIGNAL PORT |
| 摘要 |
In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type. The region of the first conductivity type can be configured to be coupled to a first node having a first voltage, and the region of the second conductivity type can be configured to be coupled to a second node having a second voltage different than the first voltage. |
| 申请公布号 |
US2014239447(A1) |
申请公布日期 |
2014.08.28 |
| 申请号 |
US201313774135 |
申请日期 |
2013.02.22 |
| 申请人 |
FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
Snowdon Kenneth P. |
| 分类号 |
H01L27/10 |
主分类号 |
H01L27/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type; and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type, the region of the first conductivity type configured to be coupled to a first node having a first voltage, the region of the second conductivity type configured to be coupled to a second node having a second voltage different than the first voltage. |
| 地址 |
San Jose CA US |
