State Machine for Low-Noise Clocking of High Frequency Clock

摘要

Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.

主权项

1. A method, comprising:
receiving a signal to adjust a clock having a first rate to a second rate, wherein the first rate is zero and the second rate is a reference clock rate, and wherein the first rate, the second rate, and a third rate are related to the reference clock rate such that the first rate equals a first multiplier times the reference clock rate, the second rate equals a second multiplier times the reference clock rate, and the third rate equals a third multiplier times the reference clock rate; ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates, wherein ramping comprises ramping up the clock from the reference clock rate divided by 7 to the reference clock rate divided by 2; dithering up the clock from the reference clock rate divided by 2 to the reference clock rate; and operating the clock at the second rate.