| 发明名称 |
METHOD OF FABRICATING SEMICONDUCTOR PACKAGE |
| 摘要 |
A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer. |
| 申请公布号 |
US2014242752(A1) |
申请公布日期 |
2014.08.28 |
| 申请号 |
US201313837179 |
申请日期 |
2013.03.15 |
| 申请人 |
SAMSUNG ELECTRONICS CO., LTD |
发明人 |
PARK Jae-Yong;KO Jun-Young;KIM Sang-Jun |
| 分类号 |
H01L23/00 |
主分类号 |
H01L23/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of fabricating a semiconductor package, the method comprising:
providing a wafer which comprises an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer. |
| 地址 |
Suwon-si KR |
