COMPACT LOW-POWER FULLY DIGITAL CMOS CLOCK GENERATION APPARATUS FOR HIGH-SPEED SERDES

摘要

A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

主权项

1. A device for high-speed clock generation, the device comprising:
an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate a plurality of clock signals with different phase angles; and a phase-interpolator (PI) circuit configured to receive the plurality of clock signals and to generate an output clock signal having a correct phase angle, wherein the PI circuit comprises at least one of:
a smoothing block configured to smooth the plurality of clock signals with different phase angles to generate a plurality of smooth clock signals; ora pulling block configured to smooth the plurality of clock signals with different phase angles and pull edges of the plurality of smooth clock signals closer to one another.