发明名称 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SAME |
摘要 |
According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be included in any of a plurality of threshold distributions, the memory cell being connected between a bit line and a source line. The control circuit, in at least one of a write verify operation and a read operation on a selected memory cell, applies to the control gate a control gate voltage to determine the threshold of the selected memory cell, the control gate voltage having a plurality of values respectively corresponded to the plurality of threshold distributions, and sets a voltage between the bit line and the source line based on the control gate voltage. |
申请公布号 |
US2014241058(A1) |
申请公布日期 |
2014.08.28 |
申请号 |
US201314017641 |
申请日期 |
2013.09.04 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
Yoshida Masashi;Takahashi Eietsu;Shiino Yasuhiro;Matsuura Nobushi |
分类号 |
G11C16/10 |
主分类号 |
G11C16/10 |
代理机构 |
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代理人 |
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主权项 |
1. A nonvolatile semiconductor memory device, comprising:
a memory cell array comprising a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be included in any of a plurality of threshold distributions and thereby store multiple bits of data, the memory cell being connected between a bit line and a source line, and the control gate of the memory cell being connected to a word line; and a control circuit that, in at least one of a write verify operation and a read operation on a selected memory cell, applies to the word line a control gate voltage to determine the threshold of the selected memory cell, the control gate voltage having a plurality of values respectively corresponded to the plurality of threshold distributions, and sets a voltage between the bit line and the source line to which the selected memory cell is connected, based on the control gate voltage. |
地址 |
Minato-ku JP |