发明名称 SEMICONDUCTOR DEVICE
摘要 A semiconductor device capable of maintaining data even after instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors. The first and fourth transistors are p-channel transistors. The second and fifth transistors are n-channel transistors. In the third and sixth transistors, a channel formation region is included in an oxide semiconductor layer. A high voltage is applied to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor. A low voltage is applied to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor.
申请公布号 US2014240634(A1) 申请公布日期 2014.08.28
申请号 US201414190278 申请日期 2014.02.26
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Matsuzaki Takanori
分类号 H01L27/12;G02F1/1368 主分类号 H01L27/12
代理机构 代理人
主权项 1. A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein: each of the first transistor and the fourth transistor is a p-channel transistor, each of the second transistor and the fifth transistor is an n-channel transistor, each of the third transistor and the sixth transistor is a transistor including an oxide semiconductor, a source of the first transistor and a source of the fourth transistor are configured to be supplied with a high voltage, a source of the second transistor and a source of the fifth transistor are configured to be supplied with a low voltage, a drain of the first transistor is electrically connected to a drain of the second transistor and a source of the third transistor, a drain of the third transistor is electrically connected to a gate of the fourth transistor and a gate of the fifth transistor, a drain of the fourth transistor is electrically connected to a drain of the fifth transistor and a source of the sixth transistor, and a drain of the sixth transistor is electrically connected to a gate of the first transistor and a gate of the second transistor.
地址 Atsugi-shi JP