MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION

摘要

A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.

主权项

1. A computer-readable storage device storing executable instructions that, in response to execution, cause a system comprising a processor to perform operations, comprising:
receive incoming data writes at a first memory device; caching at least one sector of the incoming data writes in the first memory device; and moving the at least one sector of the incoming data writes from the first memory device to the second memory device based in part on a determination that a frequently written sector is maintained in the first memory device as long as possible based on a data capacity of the first memory device, wherein the incoming data writes are written to the first memory device during a data burst and at a high rate over a short time period and the at least one sector of the incoming data writes are moved at a slower rate to the second memory device during a background operation.