| 发明名称 |
FAST READ IN WRITE-BACK CACHED MEMORY |
| 摘要 |
An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the memory by bypassing the cache in response to the location having the clean state. |
| 申请公布号 |
US2014244902(A1) |
申请公布日期 |
2014.08.28 |
| 申请号 |
US201313833127 |
申请日期 |
2013.03.15 |
| 申请人 |
LSI CORPORATION |
发明人 |
Simionescu Horia;Panda Siddartha Kumar;Sablok Kunal;Reddy Oleti Veera Kumar |
| 分类号 |
G06F12/08;G06F12/02 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a cache comprising a plurality of cache lines and configured to (i) store a plurality of data items in said cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of said cache lines, wherein said cache has a write-back policy to a memory; and a circuit configured to (i) check a location in said map corresponding to a read address of a read request and (ii) obtain read data directly from said memory by bypassing said cache in response to said location having said clean state. |
| 地址 |
San Jose CA US |
