PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING

摘要

A PLL operates in a first low bandwidth mode using a first control loop and in a second high bandwidth mode using a second control loop. The PLL includes a VCO that generates an output signal at a desired frequency used by a transmitter. When the transmitter switches from a High Power mode (HP TX) to a Low Power mode (LP TX), the PLL is perturbed (VCO no longer generates the desired frequency) and must resettle within an allocated time. In one example, the VCO frequency is 3.96 GHz and the settling time requirement is 25 microseconds. Upon switching from HP TX to LP TX, the PLL is switched to the second high bandwidth mode 15 microseconds and is then switched back to the first low bandwidth mode. The PLL resettles to within 1 ppm of the initial VCO frequency of 3.96 GHz within the allocated 25 microseconds.

主权项

1. A Phase-Locked Loop (PLL) circuit comprising:
a Voltage Controlled Oscillator (VCO) that outputs a VCO output signal; and a mode control circuit that receives a transmitter power mode control signal (TX HP/LP), wherein TX HP/LP has a transition indicative of a transmitter switching from a High Power (HP TX) mode to a Low Power (LP TX) mode, wherein the mode control circuit in response to the transition: 1) causes the PLL to switch from operating in a first low bandwidth mode to operating in a second high bandwidth mode and then to operate in the second high bandwidth mode for a high bandwidth time period (HBWTP), and 2) at an ending of HBWTP causes the PLL to switch from operating in the second high bandwidth mode to operating in the first low bandwidth mode.