THERMAL VIA FOR 3D INTEGRATED CIRCUITS STRUCTURES

摘要

A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.

主权项

1. A three dimensional (3D) integrated circuit structure comprising:
a first chip having a first dielectric layer, a first plurality of through substrate vias (TSVs) and a first plurality of pads on the first dielectric layer, the first dielectric layer formed on a bottom surface of the first chip, the pads are electrically connected to the corresponding TSVs of the first chip; a second chip having a second dielectric layer, a second plurality of TSVs, and a second plurality of pads on the second dielectric layer, the second dielectric layer formed on a bottom surface of the second chip, the pads are electrically connected to the corresponding TSVs of the second chip, the second chip disposed vertically adjacent to the first chip, wherein the bottom surface of the second chip faces the bottom surface of the first chip and wherein the pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps; and a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps, the thermal via structure having an upper portion and a lower portion, the upper portion formed in the first dielectric layer and contacting the bottom surface of the first chip and the lower portion formed in the second dielectric layer and contacting the bottom surface of the second chip.