SEMICONDUCTOR MEMORY DEVICE

摘要

A semiconductor memory device includes a memory cell array including memory cells arranged therein. A first latch circuit temporarily holds data to perform a read operation and a write operation on the memory cell array. The second latch circuit temporarily holds a control signal. A control circuit controls the memory cell array, the first latch circuit and the second latch circuit. The control circuit limits an operation of the first latch circuit in a state after an operation on the memory cell array has been finished, and limits an operation of the second latch circuit based on a command supplied from external.

主权项

1. A semiconductor memory device, comprising:
a memory cell array including memory cells arranged therein; a first latch circuit operative to temporarily hold data to perform a read operation and a write operation on the memory cell array; a second latch circuit operative to temporarily hold a control signal; and a control circuit configured to control the memory cell array, the first latch circuit and the second latch circuit, the control circuit being operative to limit an operation of the first latch circuit in a state after an operation on the memory cell array has been finished, and limit an operation of the second latch circuit based on a command supplied from external.