| 摘要 |
<p>A clock multiplier circuit (200) includes a clock generator (210), a delay element (220), a logic gate (230), and a duty cycle correction circuit (240). The clock generator (210) generates a clock signal (X). The delay element (240) generates a delayed clock signal (XDEL) in response to the clock signal. The logic gate ( 220) generates a frequency-multiplied clock signal (X2) in response to the clock signal (X) and the delayed clock signal (XDEL). Tne duty cycle correction circuit (240) generates an adjustment signal (DCA) based at least in part on the frequency-multiplied clock signal (X2). The clock generator (210) adjusts a duty cycle of the clock signal (X) in response to the adjustment signal (DCA).</p> |
