| 摘要 |
<p>Shift register comprising a plurality of stages (ST_n figure 1) each for outputting k-composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes k A-substages each for controlling a voltage at an A-set node and also on at least one A-reset node in response to an external A-control signal and generating an A-carry pulse A1-CR_n-1 based on the voltage at the A-set node, A-reset node and any A-clock pulse; a B-substage for controlling a voltage at a B-set node and B-reset node in response to an external B-control signal and generating a B-carry pulse B-CR_n-1 based on the B set and reset nodes and any B-clock pulse whereby the B-clock may have a differing frequency and pulse width to that of the A clock (figure 4); and a scan output controller (SOC figure 2) for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse (Vg1_n or Vg2_n, figure 2). The invention provides a shift register in which the set nodes are bootstrapped using clock pulses and a floating structure so that scan pulses of the composite pulses (including the A and B scan pulses) can be outputted stably despite the clock pulses being at a low voltage, hence reducing the size of the output drive devices. One embodiment (figure 9) uses MOSFET drivers in the scan output controller to combine the set (A1-Q fig 9), reset (A1-QB) of the A stage with a clock (A1-CLK) and also combine with signals derived from the B-carry pulse B-CR_n and another clock pulse BA1_CLK to form the composite pulse Vg1_n.</p> |
