Clock and mode signals for header and data communications

摘要

Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

主权项

1. A process of communicating with a communication device comprising:
A. receiving over a clock signal lead and a mode signal lead a communication device steady state signal and alternating signals indicating a message header; B. receiving over the clock signal lead and the mode signal lead a steady state signal and alternating signals indicating communication of a message; and C. receiving over one of the clock signal lead and the mode signal lead alternating signals used to receive data signals of the message on a serial data input lead of the communication device.