| 摘要 |
A shaper of a single packet comprising four three-pulse code groups with programmable time parameters multiple of a period of periodic pulse train supplied to input thereof from an output of crystal-controlled oscillator comprises a reversible count-down counter having a synchronous parallel load enable input, a counting mode enable input and an asynchronous reset, an overflow output of which is connected to a synchronous parallel setting in a state determined by variables which are supplied to parallel load inputs. A binary adder, four inverters, a comparator, first and second synchronous D-flip-flops having asynchronous reset, first and second synchronous DL-flip-flops comprising asynchronous reset; a three-input OR-NOT element, a two-input AND-NOT element, first and second two-input AND elements; a four-input OR element, a circuit comprising resistor and capacitor are introduced. |
