Computer hardware architecture and data structures for a ray traversal unit to support incoherent ray traversal

摘要

A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be accomplished by organizing the rays for minimal movement of data, hiding latency due to external memory access, and performing adaptive binning. Rays may be binned into coarse grain and fine grain spatial bins, independent of direction.

主权项

1. A method in a ray traversal unit comprising digital logic circuits, the method comprising the digital logic circuits:
storing in a data store ray data representative of a plurality of rays traversed through a scene, the scene being partitioned into a hierarchy of cells, the ray data including, for each ray, a hierarchy of dirty cells intersected by said each ray, the ray data being grouped according to intersected dirty cells at a first level in the hierarchy (“first level dirty cells”); receiving from the data store ray data representative of a group of first rays which intersect a given first level dirty cell; sorting the received ray data according to dirty cells in a second level in the hierarchy (“second level dirty cells”) and dirty cells in a third level in the hierarchy (“third level dirty cells”); processing the sorted ray data for ray/object intersections, and when a given ray intersects an object then:
completing processing of the given ray concurrently with launching one or more new rays from the given ray;traversing the one or more new rays through the scene; andwhen one of the new rays intersects a dirty cell at an nth level in the hierarchy, then storing ray data of said one of the new rays in the data store including data representative of a hierarchy of dirty cells that contain the nth level dirty cell.