发明名称 Providing metadata in a translation lookaside buffer (TLB)
摘要 In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
申请公布号 US8819392(B2) 申请公布日期 2014.08.26
申请号 US201213550817 申请日期 2012.07.17
申请人 Intel Corporation 发明人 Champagne David;Tiwari Abhishek;Wu Wei;Hughes Christopher J.;Kumar Sanjeev;Lu Shih-Lien
分类号 G06F12/10 主分类号 G06F12/10
代理机构 Trop, Pruner & Hu, P.C. 代理人 Trop, Pruner & Hu, P.C.
主权项 1. A processor comprising: a first core to execute instructions; and a first translation lookaside buffer (TLB) coupled to the first core, wherein the first TLB is to store a plurality of entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store a plurality of bits for a memory page of a main memory associated with the VA-to-PA translation, the plurality of bits to indicate at least one attribute of information in the memory page, wherein the main memory has a page frame storage area to store a plurality of page tables each having a plurality of page table entries each corresponding to a memory page and a second storage area separated in address space from the page frame storage area to store the plurality of bits for each of the page table entries, a first bit of the plurality of bits of a first state to indicate whether a corresponding memory page has been initialized.
地址 Santa Clara CA US