High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory

摘要

An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

主权项

1. A method of improving performance for a computer processor, said method comprising:
receiving in an input/output processor data and a memory access instruction from said computer processor, said memory access instruction identifying a type of memory storage task from a group of more than one different memory storage task; analyzing said memory access instruction in said input/output processor to identify said type of memory storage task; if said type of memory storage task comprises a counter adjustment then
updating a value containing recent adjustments to said counter in a higher-speed memory, andupdating a full version of said counter in a slower-speed memory if an overflow of said value containing recent adjustments to said counter occurs; and if said type of memory storage task comprises a write to a FIFO queue then
storing said data in a queue tail of said FIFO queue in said higher-speed memory, andmoving data from said queue tail to a queue body of said FIFO queue in said slower-speed memory if said queue tail is filled receiving in an input/output processor, data and multiple memory access instructions from said computer processor; said received multiple memory access instructions indicating memory access type pattern from a group of more than one different memory access type patterns that includes a first memory access type pattern and a second memory access type pattern; analyzing said received multiple memory access instructions in said input/output processor to identify said memory access type pattern; using the input/output processor to perform a first high frequency memory write task and a first low frequency memory write task in response to identification of the first memory access type pattern, wherein data written using the first low frequency memory write task is accessed less frequently than data written using the first high frequency memory write task; using the input/output processor to perform a second high frequency memory write task and a second low frequency memory write task in response to identification of the second memory access type pattern, wherein data written using the second low frequency memory write task is accessed less frequently than the second high frequency memory write task; if the memory access type pattern is the first memory access type pattern,
performing the first high frequency memory write task in a higher-speed memory; andperforming the first low frequency memory write task in a slower-speed memory; and if the memory access type pattern is the second memory access type pattern,
performing the second high frequency memory write task in the higher-speed memory; andperforming the second low frequency memory write task in the slower-speed memory.